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CY62137EV30 MoBL(R)
2-Mbit (128K x 16) Static RAM
Features
* Very high speed: 45 ns * Wide voltage range: 2.20V-3.60V * Pin-compatible with CY62137CV30 * Ultra-low standby power -- Typical standby current: 1A -- Maximum standby current: 7A
Functional Description[1]
The CY62137EV30 is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by asserting Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by asserting Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The CY62137EV30 is available in 48-ball VFBGA and 44-pin TSOPII packages.
* Ultra-low active power
-- Typical active current: 2 mA @ f = 1 MHz * Easy memory expansion with CE, and OE features * Automatic power-down when deselected * CMOS for optimum speed/power * Byte power-down feature * Offered in Pb-free 48-ball VFBGA and 44-pin TSOPII package
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
128K x 16 RAM Array
SENSE AMPS
I/O0 - I/O7 I/O8 - I/O15
COLUMN DECODER BHE WE CE OE BLE
BHE BLE
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05443 Rev. *B
*
198 Champion Court
A13 A14 A15 A16
A12
Pow er Down Circuit
CE
A11
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 14, 2006
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CY62137EV30 MoBL(R)
Pin Configurations[2, 3]
VFBGA (Top View)
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 I/O11 I/O12 I/O13 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 Vcc Vss I/O6 I/O7 NC A B C D E F G H A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
44 TSOP II (Top View)
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
Product Portfolio
Power Dissipation Product Min. CY62137EV30-45LL 2.2V VCC Range (V) Typ.[7] 3.0V Max. 3.6V 45 ns Speed (ns) Typ.[7] 2 Operating ICC (mA) f = 1MHz Max. 2.5 f = fmax Typ.[7] 15 Max. 20 Standby ISB2 (A) Typ.[7] 1 Max. 7
Note: 2. NC pins are not connected on the die. 3. Pins D3, H1, G2, and H6 in the BGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively.
Document #: 38-05443 Rev. *B
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CY62137EV30 MoBL(R)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied ........................................... -55C to + 125C Supply Voltage to Ground Potential ............................. -0.3V to 3.9V (VCC(MAX) + 0.3V) DC Voltage Applied to Outputs in High-Z State[4, 5] ............... -0.3V to 3.9V (VCC MAX + 0.3V) DC Input Voltage[4, 5] ........... -0.3V to 3.9V (VCC MAX + 0.3V) Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA
Operating Range
Device Range Ambient Temperature VCC[6]
CY62137EV30-45LL Industrial -40C to +85C 2.2V to 3.6V
Electrical Characteristics Over the Operating Range
Test Conditions Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage IOH = -0.1 mA IOH = -1.0 mA Output LOW Voltage Input HIGH Voltage Input LOW Voltage IOL = 0.1 mA IOL = 2.1mA VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled VCC = VCCmax IOUT = 0 mA CMOS levels VCC = 2.20V VCC = 2.70V VCC = 2.20V VCC = 2.70V 1.8 2.2 -0.3 -0.3 -1 -1 15 2.0 1 Min. 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 20 2.5 7 A 45 ns Typ.[7] Max. Unit V V V V V V V V A A mA
VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz Automatic CE Power-down Current -- CMOS Inputs Automatic CE Power-down Current -- CMOS Inputs
ISB1
CE1 > VCC - 0.2V, CE2 < 0.2V VIN > VCC - 0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), f = 0 (OE and WE), VCC = 3.60V CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V
ISB2
1
7
A
Notes: 4. VIL(min.) = -2.0V for pulse durations less than 20 ns. 5. VIH(max)=VCC+0.75V for pulse durations less than 20ns. 6. Full Device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after VCC stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
Document #: 38-05443 Rev. *B
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CY62137EV30 MoBL(R)
Capacitance (for all packages)[8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max. 10 10 Unit pF pF
Thermal Resistance
Parameter JA JC Description Thermal Resistance (Junction to Ambient)[8] Thermal Resistance (Junction to Case)[8] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA 75 10 TSOP II 77 13 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE Parameters R1 R2 RTH VTH 2.50V 16667 15385 8000 1.20 R2 VCC 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V 3.0V 1103 1554 645 1.75 Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC= 1V CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1 0.8 3 Typ.[7] Max. Unit V A
tCDR[8] tR[9]
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Data Retention Waveform[10]
DATA RETENTION MODE VCC CE or BHE.BLE
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
Notes: 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
Document #: 38-05443 Rev. *B
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CY62137EV30 MoBL(R)
Switching Characteristics Over the Operating Range [11]
45 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[14] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to WE HIGH to High-Z[12, 13] Low-Z[12] 10 45 35 35 0 0 35 35 25 0 18 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to LOW Z
[12]
Description
Min. 45
Max.
Unit ns
45 10 45 22 5 18 10 18 0 45 45 5 18
ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z[12, 13] CE LOW to Low Z[12] CE HIGH to High Z[12, 13] CE LOW to Power-Up CE HIGH to Power-Down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[12] BLE/BHE HIGH to HIGH Z[12, 13]
Notes: 10. BHE.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 13. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high- impedance state. 14. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05443 Rev. *B
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CY62137EV30 MoBL(R)
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[15, 16] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)[16, 17]
ADDRESS
CE tACE OE tDOE BHE/BLE tLZOE
tRC tPD tHZCE
tHZOE
tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB ICC DATA VALID HIGH IMPEDANCE
Notes: 15. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 16. WE is HIGH for read cycle. 17. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
Document #: 38-05443 Rev. *B
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CY62137EV30 MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[14, 18, 19]
tWC ADDRESS tSCE CE tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 20 tHZOE DATAIN tHD
Write Cycle No. 2 (CE Controlled)[14, 18, 19]
tWC ADDRESS tSCE CE
tSA
tAW tPWE
tHA
WE
BHE/BLE
tBW
OE tSD DATA I/O NOTE 20 tHZOE DATAIN tHD
Notes: 18. Data I/O is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state. 20. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05443 Rev. *B
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CY62137EV30 MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[19]
tWC ADDRESS tSCE CE
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATAI/O NOTE 20 tHZWE DATAIN
tHD
tLZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19]
tWC ADDRESS
CE tSCE
tAW BHE/BLE tSA WE
tHZWE
tHA tBW
tPWE tSD DATAIN
tLZWE tHD
DATA I/O
NOTE 20
Document #: 38-05443 Rev. *B
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CY62137EV30 MoBL(R)
Truth Table
CE H X L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High Z High Z Data Out (I/OO-I/O15) Data Out (I/OO-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z High Z Data In (I/OO-I/O15) Data In (I/OO-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0-I/O7 in High Z Mode Deselect/Power-down Deselect/Power-down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 45 45 Ordering Code CY62137EV30LL-45BVXI CY62137EV30LL-45ZSXI Package Diagram Package Type Operating Range Industrial
51-85150 48-ball Very Fine Pitch BGA (6 mm x 8mm x 1 mm) (Pb-free) 51-85087 44-pin TSOP II (Pb-free)
Document #: 38-05443 Rev. *B
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CY62137EV30 MoBL(R)
Package Diagrams
48-pin VFBGA (6 x 8 x 1 mm) (51-85150)
TOP VIEW
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B
A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C
51-85150-*D
SEATING PLANE 0.26 MAX. C 1.00 MAX
Document #: 38-05443 Rev. *B
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CY62137EV30 MoBL(R)
Package Diagrams (continued)
44-Pin TSOP II (51-85087)
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05443 Rev. *B
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62137EV30 MoBL(R)
Document History Page
Document Title: CY62137EV30 MoBL(R) 2-Mbit (128K x 16) Static RAM Document Number: 38-05443 REV. ** *A ECN NO. Issue Date 203720 234196 See ECN See ECN Orig. of Change AJU AJU Description of Change New Data Sheet Changed ICC MAX at f=1MHz from 1.7 mA to 2.0 mA Changed ICC TYP from 12 mA (35 ns speed bin) and 10 mA (45 ns speed bin) to 15 mA and 12 mA respectively Changed ICC MAX from 20 mA (35 ns speed bin) and 15 mA (45 ns speed bin) to 25 mA and 20 mA respectively Changed ISB1 and ISB2 TYP from 0.6 A to 0.7 A Changed ISB1 and ISB2 MAX from 1.5 A to 2.5 A Changed ICCDR from 1 A to 2 A Fixed typos on TSOP II pinout: Pin 18-22: address lines Pin 23: NC Added Pb-free information Converted from Advanced Information to Final. Removed 35 ns Speed Bin Removed "L" version Changed ball E3 from DNU to NC. Removed the redundant footnote on DNU. Moved Product Portfolio from Page # 3 to Page #2. Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax=1/tRC Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values from 2.5 A to 7 A. Changed VCC stabilization time in footnote #7 from 100 s to 200 s Changed the AC test load capacitance from 50pF to 30pF on Page# 4 Changed VDR from 1.5V to 1V on Page# 4. Changed ICCDR from 2 A to 3 A. Added ICCDR typical value. Corrected tR in Data Retention Characteristics from 100 s to tRC ns Changed tOHA , tLZCE and tLZWE from 6 ns to 10 ns Changed tLZBE from 6 ns to 5 ns Changed tLZOE from 3 ns to 5 ns Changed tHZOE, tHZCE, tHZBE and tHZWE from 15 ns to 18 ns Changed tSCE,tAW and tBW from 40 ns to 35 ns Changed tPWE from 30 ns to 35 ns Changed tSD from 20 ns to 25 ns Updated the Ordering Information table and replaced the Package Name column with Package Diagram.
*B
427817
See ECN
NXR
Document #: 38-05443 Rev. *B
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